// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: ${module_instance_name}

  // Top level dut name (sv module).
  dut: ${module_instance_name}

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: xcelium

  // Fusesoc core file used for building the file list.
  fusesoc_core: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sim:0.1")}

  // Testplan hjson file.
  testplan: "{self_dir}/../data/pwm_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{self_dir}/../data/${module_instance_name}.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["${module_instance_name}_bind", "sec_cm_prim_onehot_check_bind"]

  // Coverage exclusion
  xcelium_cov_refine_files: ["{self_dir}/cov/pwm_unr_excl.vRefine"]

  overrides: [
    {
      // Override the base ccf coverage configuration file for the "default" build mode (used for tests
      // other than the CSR tests). This will include the default cover.ccf file as its first item.
      name: default_xcelium_cov_cfg_file
      value: "{self_dir}/cov/cover.ccf"
    }
  ]

  // Default iterations for all tests - each test entry can override this.
  reseed: 25

  component_a: "uvm_test_top.env.scoreboard"
  id_a: _ALL_
  verbosity_a: UVM_HIGH
  phase_a: run
  run_modes: [
    {
      name: set_verbosity_comp_a_uvm_high
      run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}"]
    }
  ]

  run_opts: [
    "+cdc_instrumentation_enabled=1",

    // Use a short enough timeout for a standard test. This is essentially driven by NUM_CYCLES,
    // which is slightly over 1e6. The DV_COMMON_CLK_CONSTRAINT macro in dv_macros.svh guarantees a
    // frequency of at least 5MHz. At a clock frequency of 5MHz, we'd expect 1e6 cycles to take
    // 0.2 seconds, so we set the timeout to 0.3 seconds.
    "+test_timeout_ns=300_000_000"
  ]

  // Default UVM test and seq class name.
  uvm_test: pwm_base_test
  uvm_test_seq: pwm_base_vseq

  // List of test specifications.
  tests: [
    {
      name: pwm_smoke
      uvm_test_seq: pwm_smoke_vseq
      reseed: 10
    }
    {
      name: pwm_rand_output
      uvm_test_seq: pwm_rand_output_vseq
    }
    {
      name: pwm_heartbeat_wrap
      uvm_test_seq: pwm_heartbeat_wrap_vseq
      // We don't need many seeds of this test: it will exercise
      // identical code across the different channels anyway.
      reseed: 10
    }
    {
      name: pwm_perf
      uvm_test_seq: pwm_perf_vseq
      reseed: 10
    }
    {
      name: pwm_phase
      uvm_test_seq: pwm_phase_vseq
    }
    {
      name: pwm_regwen
      uvm_test_seq: pwm_regwen_vseq
      // A single seed suffices because we constrain the configuration such that the PWM outputs
      // are definitely changing and monitors/scoreboard are predicting their behavior. The sequence
      // always clears the `regwen` and coverage will confirm that prohibited writes were attempted.
      reseed: 1
    }
    {
      name: pwm_stress_all
      uvm_test_seq: pwm_stress_all_vseq
      run_opts:["+test_timeout_ns=10_000_000_000"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["pwm_smoke"]
    }
  ]
}
